update

css/approaching.css

@@ -185,11 +185,12 @@
 .futureList.en .futureContent p:nth-child(2) {
     width: 96%;
     /* font-weight: bold; */
-    font-size: 1vw;
+    font-size: 0.9vw;
     text-align: left;
     line-height: 2.7vh;
     font-family: 'Segoe UI', 'Arial', 'Helvetica', sans-serif;
  
+   
 }
 
 .futureList.en .futureCircleInner  {

html/approaching.html

@@ -75,10 +75,10 @@
      <section class="future">
         <ul class="futureList">
             <li>
-                <img class="futureImg" src="../imgs/approaching/ai.png" alt="AI加速芯片">
+                <img class="futureImg" src="../imgs/approaching/ai.png" alt="定制加速芯片">
                 <div class="futureContent">
                     <p>持续迭代与优化</p>
-                    <p>聚焦AI加速芯片的高效能、低延迟与低功耗优化，支持智能终端、边缘计算和行业应用的多场景落地。持续推进自研IP核、算子优化和软硬件协同设计，提升芯片整体性能与能效比。</p>
+                    <p>聚焦定制加速芯片的高效能、低延迟与低功耗优化，支持智能终端、边缘计算和行业应用的多场景落地。持续推进自研IP核、算子优化和软硬件协同设计，提升芯片整体性能与能效比。</p>
                 </div>
                 <div class="futureCircle">
                     <div class="futureCircleInner">

html/ourProducts.html

@@ -188,7 +188,7 @@
                         <div class="info-list">
                             <!-- <p>客户需求：由于客户业务的急剧扩大，客户希望在S1PRO基础上出一个性能更强、功耗更低的芯片。</p> -->
                             <p class="detail_info_textS6PRO1">解决方案：在S1PRO芯片的架构基础上进一步优化细节，缩减逻辑资源，节省面积。</p>
-                            <p class="detail_info_textS6PRO2">技术亮点：使用了定制化的12nm工艺，集成了多个核心模块，并通过自研AI算法加速模块，提升了AI运算能力。</p>
+                            <p class="detail_info_textS6PRO2">技术亮点：使用了定制化的12nm工艺，集成了多个核心模块。</p>
                         
                         </div>
                     </div>

js/approaching.js

@@ -9,9 +9,9 @@ document.addEventListener('DOMContentLoaded', function () {
             // 列表
             futureList: [
                 {
-                    imgAlt: "AI加速芯片",
+                    imgAlt: "定制加速芯片",
                     title: "持续迭代与优化",
-                    desc: "聚焦AI加速芯片的高效能、低延迟与低功耗优化，支持智能终端、边缘计算和行业应用的多场景落地。持续推进自研IP核、算子优化和软硬件协同设计，提升芯片整体性能与能效比。",
+                    desc: "聚焦定制加速芯片的高效能、低延迟与低功耗优化，支持智能终端、边缘计算和行业应用的多场景落地。持续推进自研IP核、算子优化和软硬件协同设计，提升芯片整体性能与能效比。",
                     circle: "应用领域"
                 },
                 {
@@ -39,9 +39,9 @@ document.addEventListener('DOMContentLoaded', function () {
             // 列表
             futureList: [
                 {
-                    imgAlt: "AI Acceleration Chip",
+                    imgAlt: "Customized acceleration chip",
                     title: "Continuous Iteration & Optimization",
-                    desc: "Focus on high performance, low latency, and low power optimization of AI acceleration chips, supporting multi-scenario applications in smart terminals, edge computing, and industries. Continuously promote self-developed IP cores, operator optimization, and hardware-software co-design to improve overall chip performance and energy efficiency.",
+                    desc: "Focusing on the high efficiency, low latency and low power optimization of customized acceleration chips, it supports the landing of intelligent terminals, edge computing and industrial applications in multiple scenarios. Continuously promote self-developed IP cores, operator optimization, and software hardware collaborative design to improve the overall performance and energy efficiency ratio of chips.",
                     circle: "Application Field"
                 },
                 {

js/ourProducts.js

@@ -120,9 +120,9 @@ document.addEventListener('DOMContentLoaded', function() {
             detail_info_textY1001:"解决方案：我们通过对客户需求的深度研究，设计了一款集成了高速计算、信号处理单元和数据传输功能的芯片。",
             detail_info_textY1002:"技术亮点：采用了定制化的22nm工艺，低功耗设计。",
             detail_info_textS6PRO1:"解决方案：在S1PRO芯片的架构基础上进一步优化细节，缩减逻辑资源，节省面积。",
-            detail_info_textS6PRO2:"技术亮点：使用了定制化的12nm工艺，集成了多个核心模块，并通过自研AI算法加速模块，提升了AI运算能力。",
+            detail_info_textS6PRO2:"技术亮点：使用了定制化的12nm工艺，集成了多个核心模块，并通过自研算法加速模块，提升了运算能力。",
             detail_info_textS1PRO1:"解决方案：我们根据客户的需求设计了一个集成soc和特定加速模块的系统级芯片。通过先进的架构和特定的低功耗设计，确保芯片在性能和功耗上的平衡。",
-            detail_info_textS1PRO2:"技术亮点：使用了定制化的22nm工艺，集成了多个核心模块，并通过自研AI算法加速模块，提升了AI运算能力。",
+            detail_info_textS1PRO2:"技术亮点：使用了定制化的22nm工艺，集成了多个核心模块，并通过自研算法加速模块，提升了运算能力。",
             detail_info_textVV101:"解决方案：我们根据客户的需求设计了一个由CPU核心处理器连接外部存储并通过私有总线扩展外设接口，内部包含两个RAM，具备ITCM和DTCM用于指令和数据存储。",
             detail_info_textVV102:"技术亮点：EAI协处理器接口和AES算法核支持高效加解密运算，RSA算法核由控制、模乘和寄存器堆组成，实现高效RSA算法运算。",
             detail_info_textFX1001:"解决方案：我们根据客户的需求设计了一个由两个Master和三个Slave组成，其中，两个Master分别是CPU内核和DMA控制器，三个Slave为内部SRAM，NVM和外设。",
@@ -153,9 +153,9 @@ document.addEventListener('DOMContentLoaded', function() {
             detail_info_textY1001:"Solution: We designed a chip that integrates high-speed computing, signal processing unit and data transmission functions through an in-depth study of customer requirements.",
             detail_info_textY1002:"Technical highlight: Adopting customized 22nm process and low-power design.",
             detail_info_textS6PRO1:"Solution: Further optimize the details based on the architecture of the S1PRO chip, reduce logic resources and save area.",
-            detail_info_textS6PRO2:"Technical highlights: it uses a customized 12nm process, integrates multiple core modules, and improves AI computing power with a self-developed AI algorithm acceleration module.",
+            detail_info_textS6PRO2:"Technical highlights: Customized 12nm process is used, multiple core modules are integrated, and self-developed algorithm acceleration modules are used to enhance computing power.",
             detail_info_textS1PRO1:"Solution: We designed a system-on-chip with integrated soc and specific acceleration modules according to the customer's requirements. The advanced architecture and specific low-power design ensure that the chip is balanced in terms of performance and power consumption.",
-            detail_info_textS1PRO2:"Technical highlights: it uses a customized 22nm process, integrates multiple core modules, and improves AI computing power with a self-developed AI algorithm acceleration module.",
+            detail_info_textS1PRO2:"Technical highlights: Customized 12nm process is used, multiple core modules are integrated, and self-developed algorithm acceleration modules are used to enhance computing power.",
             detail_info_textVV101:"Solution: According to the customer's requirements, we designed a CPU core processor to connect to external storage and extend the peripheral interface through a private bus, which contains two internal RAMs with ITCM and DTCM for instruction and data storage.",
             detail_info_textVV102:"Technology highlights: EAI coprocessor interface and AES algorithm core support efficient encryption and decryption operations, RSA algorithm core consists of control, modulo multiplication and register stacks to realize efficient RSA algorithm operations.",
             detail_info_textFX1001:"Solution: According to the customer's requirements, we designed a system consisting of two Masters and three Slaves, where the two Masters are the CPU core and the DMA controller, and the three Slaves are the internal SRAM, NVM and peripherals.",