Personally I don’t assume we are going to see the road between memory and storage be all that muddled sooner or later. Yes, Memory Wave 3D XPoint is much more responsive than Flash. But Flash isn’t all that impressive as is. The typical onerous drive has access latencies round 4ms on average. Flash can reach nicely bellow µs latency, but for very small arrays. That is expensive and principally seen in Microcontrollers that execute immediately from their Flash. "Enterprise grade" flash that optimizes at price/GB may have far larger latency, in the few to tens of µs region. 3D Xpoint is a little bit of a wash. I've seen quoted figures of sub 350ns write latency, but that is likely for a single cell, not an array. Optane modules from Intel then again have typical latencies round 5-15µs, however that is from a "system" perspective, ie, protocol and controller overhead comes into play, as well as one’s software environment.
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DRAM alternatively has entry latencies round 2-15ns at current. The problem with latency is that it leads to our processor stalling attributable to not getting the info in time. One can prefetch, however branches makes prefetching tougher, since what side must you fetch? Department prediction partly solves this issue. However from a performance standpoint, we should fetch both sides. But when now we have more latency, we have to prefetch even earlier, risking extra branches. In other words, peak bandwidth required by our processor will increase at an exponential price compared to latency. A charge that's utility dependent as nicely. Caching might sound like the trivial resolution to the issue, but the effectivity of cache is proportional to the latency. To a level, cache is a magic bullet that simply makes memory latency disappear. But every time an software requires one thing that isn’t in cache, then the applying stalls, as long as there's threads to take its place that also have knowledge to work on, then you definitely won’t have a efficiency deficit other than thread switching penelties, however for those who don’t have such threads, then the CPU stalls.
One can be sure that more threads have their data by just making the cache bigger, but cache is loads more expensive than DRAM. In the end, all of it leads to the truth that increasing latency would require an arbitrary quantity extra cache for an analogous system performance. Going from the few ns latency of DRAM to the couple of µs latency of current persistent Memory Wave System just isn't sensible as an precise substitute for DRAM, even when it reduces its latency to a a hundredth it remains to be not impressive so far as memory goes. Though, the usage of persistent DIMMs for storage caching or as a "RAM drive" of kinds still has main advantages, however for program execution it's laughable. And that i don’t suspect this to vary any time soon. But I can see a future the place the primary memory relocates into the CPU. Where the CPU itself has an HBM memory chip or four on it supplying relatively low latency and high bandwidth memory to the CPU, whereas the exterior buses are used for IO and storage. But this isn’t all that reasonable in more skilled purposes, since some workstation purposes truthfully needs 10’s-100’s of GB of actual RAM to get good performance.
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